Data transfer control apparatus and method

ABSTRACT

An improved data transfer system enables a common data source to operate asynchronously with a plurality of different data receivers at a data transfer rate that is limited only by the operating rates of the data receivers and the data source. The operating conditions of the data receivers are sensed in common by the data source and the operating condition of the data source is sensed by the data receivers in order to optimize the data transfer rate without loss of data and without restriction to a predetermined (or synchronous) data transfer rate.

BACKGROUND OF THE INVENTION

Certain known data transfer systems use data lines for the transfer ofboth data and addressing information between a source and a plurality ofreceiving modules. These systems require that all receiving modulesoperate momentarily in a common address-receiving condition to assurethat subsequently-appearing data signals may be applied to the properreceiving modules. The timing restrictions thus imposed generally limitthe data transfer operation to a sequence of events, each of which mustbe performed within specified time periods and usually restricts thedata transfer to only one receiving module at a time.

SUMMARY OF THE INVENTION

In accordance with the present invention, the conditions of all datareceivers are sensed in common to determine that all such receivers are"ready for data" (RFD), and thereafter that all such receivers have"received data" (DAC). The present invention recognizes that differentdata receivers such as output displays, printers, encoders and the like,generally have different response times to applied data signals, andthat such receivers may also require different periods of operationbefore being ready again to respond to newly applied data signals.Accordingly, each data receiver includes circuitry for indicating thatit has received the applied data signals and also for indicating when itis ready to receive new data signals after completing its operation onthe data signals previously applied.

DESCRIPTION OF THE DRAWING

FIG. 1 is a flow chart showing the operating states of the data sourceand data receivers, according to the present invention;

FIG. 2 is a schematic diagram of one embodiment of the data transferapparatus of the present invention;

FIG. 3 is a schematic diagram of typical collector logic circuitry thatmay be used as the distributed gates for the control lines of theapparatus of FIG. 2; and

FIG. 4 is a graph showing the interaction as a function of time betweendata source and receivers in the apparatus of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the flow chart of FIG. 1, the operation of the presentdata transfer system can be considered from three points of view,namely; from the data source or device that generates the data to betransferred; from the data receiver; and from the interaction betweenthe data source and the data receiver or receivers.

First, with respect to the data source, this device begins its operationby setting a DAV line 9 to the "high" logic state. This initializes thesequence. Next, the data source generates the data 11 by whatever meansit uses. For example, a counter may output data from its displayregister as later described with respect to FIG. 2. In a serial-displayregister or scanning-type display, the data for each digit display maybe available sequentially as the data per digit is multiplexed onto thedata lines. Data is thus applied to data lines through suitable driversby a source of this type. A selected period of time is required to allowthe data to settle down on the data lines. This takes into account suchmatters as signal rise and fall times, propagation delays, reflectionson the data lines and the like. The data is valid only after suchtransient conditions have settled down. The data receivers arerestricted to operation on data only while the data is valid. When thedata source determines that the data is valid 13, it must then determinewhether the receivers are ready to accept data 15. The "ready for data"(RFD) signal is produced in the manner as later described in connectionwith FIG. 3 when all receivers on the line are ready for data. If anyone or more of the receivers are not ready for data, the RFD signal willbe "low;" and when all receivers are ready, the RFD signal will be"high" (by the convention selected for this illustrated embodiment). Thedata source may then proceed by setting the DAV .[.line.]. .Iadd.signal.Iaddend."low" 17 which indicates to all of the receivers that the dataon the lines is now valid and may be accepted any time thereafter. Thedata source waits for all of the receivers to accept the data 19. Whenall of the receivers have accepted the data, a "data accepted" (DAC)signal is produced in the manner later described in connection withFIGS. 2 and 3. When the data source senses the DAC signal indicatingthat all of the receivers have accepted the data, the source then setsthe DAV .[.line.]. .Iadd.signal .Iaddend."high" 21, thereby indicatingthat the data is being removed and will no longer be valid. The sourcethen finishes 23 or repeats the cycle by returning to thegenerate-new-data phase and repeating the entire sequence of eventspreviously described.

With respect to the data receivers, each receiver starts by initializingtwo signals (RFD, DAC) to the "low" state 25. The receiver indicateswhen it is ready to accept data 27 by setting its RFD signal "high" 29.This may occur, for example, after a printer motor has to come up tospeed, or after a paper tape punch pawl has returned to its restposition, or the like. When the receiver is ready to accept the data andhas produced its RFD signal, no operation will occur until the DAVsignal appears, indicating that the data on the line is valid. Thereceiver senses the DAV .[.line.]. .Iadd.signal .Iaddend.31 to determinewhen that .[.line.]. .Iadd.signal .Iaddend.goes "low" as an indicationthat the data on the line is now valid or meaningful. The receiver thenaccepts the data 33 at any time thereafter and also sets RFD "low" 35 toindicate that the receiver is no longer ready to receive data. After thereceiver has received the data (which it may do according to its owndata transfer rate), it indicates that the "data is accepted" (DAC), bysetting the DAC .[.line.]. .Iadd.signal .Iaddend."high" 37. After thatoperation, the receiver responds further only after the source has setthe DAV .[.line.]. .Iadd.signal .Iaddend."high" again indicating thatthe data has been removed. When the receiver senses that the DAV.[.line.]. .Iadd.signal .Iaddend.goes "high" 39, the receiver sets the"data accepted" (DAC) .[.line.]. .Iadd.signal .Iaddend."low" 41 andreturns to the beginning of the cycle for a subsequent data transferoperation.

With respect to the interaction between a data source and one or moredata receivers, the operating states of the devices are sensed byinterrogating .Iadd.43-49 .Iaddend.the signals produced on three controllines during each state of operation. The source drives the data-valid(DAV) .[.line.]. .Iadd.signal .Iaddend.to .[.signal.]. .Iadd.indicate.Iaddend.the validity of the data on the data lines. A receiverinterrogates .Iadd.43 .Iaddend.the DAV line .[.43.]. to determine whenit may accept the data. The receiver also .[.signals.]. .Iadd.indicates45, 47 .Iaddend.its ability to accept data and its readiness for newdata using the RFD and DAC signals .[.45, 47.]. respectively. The sourceinterrogates these two signals to determine if it may proceed to itsnext step. Each operating step of each device is conditioned upon theexecution of a preceding operating step by the other device, asindicated in FIG. 1 by the dotted lines 45-49 between the operations andqualifiers of source and receivers. In this way, a source and aplurality of receivers are synchronized for operation at aself-determined data transfer rate.

The present data transfer system avoids transfer blockages or "hang-ups"of the entire system under conditions where all of the receivers are noton the line due, for example, to a cable disconnect or power failure, orthe like. In this condition, the RFD and DAC lines of the data receiverswill revert to the "high" state where the logic elements used are of atype subsequently described in FIG. 3 selected for this illustratedembodiment that assumes the "high" state under the conditions of a cabledisconnect or a power failure or the like. A source operating accordingto the algorithm of the present invention (shown in the left-hand sideof FIG. 1) under the above conditions will race through that sequence ofoperations as if the receivers were present and accepting the datanormally, thereby preventing a "hang-up" condition which would inhibitoperation of remaining data receivers. In addition, if any one or more,but not all, of the receivers is inoperative and has set RFD and DAC"high," it will not effect the operation of the other receivers. Incontrast, conventional data transfer systems usually stall in anoperating state waiting for the receiver, which has become inoperativedue to disconnection or power failure or the like, to accept the data.Alternatively, the source operating algorithm may be modified, as shownat 50 in FIG. 1, to include an interrogation of both RFD and DAC linesto determine the presence of the common "high" condition on these linesas being indicative of an error condition (ie., a receiver cannotphysically be both ready for data and have accepted data). Thus, inaccordance with the present invention, a source and multiple receiversof various response or operating speeds can be combined for datatransfers therebetween at transfer rates determined only by the slowestof the devices involved.

Referring now to FIG. 2, there is shown a simplified schematic diagramof the data transfer apparatus of the present invention. The apparatusincludes data source 60 and a plural number of data receivers 62, 64etc. The data source may include a counter having a plurality of outputregisters 66, 68, 70, 72 as a portion of the output circuitry of thecounter. Each of these output registers is coupled to a multiplexer 74which is driven by a two-bit counter circuit 76 such that the datasignals from each of the registers 66-72 is supplied in sequence over mlines of the data lines 78 in response to each of the four states of thecounter 76. The data source 60 also includes logic circuitry forproviding a signal on the data-valid line (DAV) in response to a logicalcombination of the signals appearing on the "ready for data" (RFD) and"data accepted" (DAC) lines.

Each of data receivers 62, 64 etc. may include suitable means operativeupon the data signal on lines 78 and in general may include remotedisplay devices, paper tape punchers, card punchers, printers, and thelike. In the illustrated embodiment, there is shown a remote displaydevice including a plurality of glow-discharge numerical indicators 80,82, 84 and 86, each driven by its respective display drivers 88, 90, 92and 94. This data receiver may be operated to actuate the outputindicators 80-86 in sequence using the time multiplexed data signalsappearing on the data lines 78 clocked into successive registers of theshift register 100 in a fashion to be described hereinafter. Each of theregisters 102, 104, 106, 108 of the shift register 100 may be a D-typeflip-flop simply arranged to operate as a shift register having a singledata input port capable of accepting m lines of data signals. Each datareceiver also includes logic elements for producing at its own responserate the "ready for data" (RFD) signals and "data accepted" (DAC)signals in response to reception of the data and the "data-valid" (DAV)signal appearing on lines 78 and 79. These signals are coupled in commonvia distributed gates 110, 112 shown in dotted form in FIG. 2 to thecommon lines 81 and 83 that are connected to the data source 60. Thesegates may be distributed in the data receiver or may be accumulated at acentral point along these control lines where convenient, and may simplyinclude conventional transistor-collector logic circuitry as shown inFIG. 3.

In operation, the data transfer apparatus of the present invention maybe considered first from the standpoint of the data source 60. At theend of a suitable operating period, data may be accumulated in each ofthe output registers 66-72 ready for distribution to the data receivers62, 64 etc. The additional logic circuitry 114 associated with the datasource 60 may be conveniently located with the data source to convert itfrom a standard source .Iadd.to a source .Iaddend.suitable for operationin accordance with the data transfer apparatus of the present invention.This additional logic circuitry 114 may be considered as controlling theoutput of data from registers 66-72 onto the data lines 78 in responseto the appearance of signal on the DAC line 83. This causes the two-bitcounter 76 to operate that multiplexer 74 for establishing data signalson data line 78 which are representative of the operating conditionsonly of register 66. At the same time, the "data accepted" (DAC) signalis delayed through delay circuit 116, and the resulting delayed signaland a "ready for data" (RFD) signal appearing on line 81 are gatedthrough gate 118 to the pair of OR gates 120, 122 cross-coupled as aflip-flop. This flip-flop produces a steady signal applied throughdriver amplifier 124 to the "data-valid" (DAV) line 79 a brief delayedtime (determined by the delay circuit 116) after appearance of datasignals on line 78. This delay interval allows such transient conditionsas propagation delays of data signals along the line 78, reflections,and the like, to settle down immediately following introduction of newdata signals on the lines 78. Thus, after the data signals have settled,the signal on DAV line 79 establishes that data is valid and can beaccepted by the data receivers 62, 64, etc.

The DAV signal appearing on line 79 is sensed by the data receiver 62 tointroduce a signal at gate 111 which is used to clock the data into thefirst register 102 of the shift register 100. The DAV signal appearingon line 79 is delayed by the first delay circuit 113 in the datareceiver 62 to enable gate 111 and also to initiate a second delay inthe time required for signal to appear on line 115. The second-delayedsignal is determined by delay circuit 117. The twice-delayed signal online 115 thus provides indication that the data has been accepted by thedata receiver 62. Also, the output of gate 111 is applied to clock thedata signal into the first register 102 of shift register 100. Thesignal on line 115 is further delayed by delay circuit 119, after whichdelay the combination of the signal once delayed by delay circuit 113and the signal three-times delayed by the additional delays of circuits117 and 119 are applied to gate 121 which produces a signal indicativeof the fact that data receiver 62 is again ready for data.

Considering the data source 60 once again, it will be apparent that the"data accepted" (DAC) signal produced by the data receiver 62 triggersthe bit count counter 76 to the next state which causes the multiplexerthen to output data on lines 78 which is representative of the operatingcondition of output register 68. Thereafter, and in response to the"ready for data" (RFD) signal appearing on RFD line 81, the data source60 again indicates that the data signals on lines 78 are valid byproducing the "data-valid" (DAV) signal on line 79. This causes the datareceiver 62 to shift the data signals first applied to the register 102of the shift register 100 to the subsequent register 104 and to applythe new data representative of the operating condition of the outputregister 68 of the data source 60 into the first register 102 of theshift register 100. The logic circuitry 125 associated with the datareceiver 62 again produces the "data accepted" (DAC) signal which isapplied via the distributed gate 110 to the DAC control line 83. Thelogic circuitry 125 also produces a "ready for data" (RFD) signal whichis applied via the distributed gate 112 to the RFD control line 81 inthe manner as previously described in connection with application ofdata signals to the register 102 in the first cycle of operation.

The operation of the data transfer apparatus according to the presentinvention thus continues in this manner until data signalsrepresentative of each of the operating conditions of output registers66-72 are applied to the corresponding registers 102-108 of the shiftregister 100. The data representative of the operating condition ofregister 66 thus appears in register 108 and the data representative ofthe operating conditions of output register 72 appears in the register102. The data present in the registers 102-108 of the shift register 100may be converted by conventional circuitry to suitable code for drivingthe output display devices 80-86. Similarly, the fourth state ofoperation of the bit count counter 76 may thus be separately channeledto counter control apparatus of the data source 60 for introducing a newset of data signals into the output registers 60-72.

While only one data receiver 62 is described herein in detail, it shouldbe apparent that other data receivers, which may operate according toconventional means, may be modified, for example, by including logiccircuitry similar to the circuitry indicated generally at 125 for thepurpose of responding to "data-valid" (DAV) signals appearing on line 79and for producing "ready for data" (RFD) signals to be applied tocontrol line 81 for producing "data accepted" (DAC) signals to beapplied to control line 83. Where a plurality of data receivers isinvolved, each having a different time of response to data signalsapplied thereto, it should be understood that the "data accepted" (DAC)signal that appears on line 83 and that is applied to the logiccircuitry 114 of the data source only appears when all data receivers62, 64, etc. have accepted the data. It should be noted that the "readyfor data" (RFD) signal that appears on line 81 for application to thelogic circuitry 114 of the data source 60 only appears when all the datareceivers 62, 64, etc. are ready for data. Operation of the datatransfer apparatus of the present invention in this fashion thus assuresthat the data transfer may progress through a series of data transfersteps at a rate which is only limited by the slowest one of the datareceivers present in the system. This obviates the need for synchronousoperation of all data receivers simultaneously and within the samepredetermined time periods of operations.

In addition, the data source 60 may include an AND gate 126 to detectboth RFD and DAC being high which indicates an error condition, since areceiver device cannot be both ready for data and accepting at the sametime. Such an error condition may be due to a cable disconnect, powerfailure or the like.

Referring now to FIG. 4, there is shown a graph of operating waveformspresent in the data transfer apparatus of FIG. 2. At a given time in theoperating cycle, one receiver 62 may signal that it is ready for dataRFD. However, it is only after .Iadd.all .Iaddend.receivers 62, 64, etc.are ready for data that the RFD signal A is produced on line 81 by agating circuit 112 of the type, for example, as shown in FIG. 3. Thelogic equation for this operation is thus:

    RFD (on line 81)= (RFD from receiver 1) (RFD from receiver 2)

    (RFD from receiver n)                                      .Iadd.(Eq. 1)

Data signals which are produced on lines 78 by the data source 60 arenot accepted by the receivers 62, 64, etc. until the data source 60produces a data-valid (DAV) output B on line 79 after appearance of theRFD signal on line 81. Thereafter, the data receivers 62, 64, etc.accept the data and, because they are accepting the data, can no longerbe ready for data. The first one of the data receivers 62, 64, etc. torespond to the data signals and the data-valid signal on line 79 willproduce an RFD signal C which removes the RFD signal from line 81.

At a later time, the fastest one of the data receivers will produce aDAC (data accepted) signal. However, it is only after all data receivershave accepted data that the DAC signal D is produced on line 83 by thegating circuit 110 of the type, for example, as shown in FIG. 3. Thelogic equation for this operation is thus:

    DAC (on line 83)= (DAC from receiver 1) (DAC from receiver 2)

    (DAC from receiver n)                                      .Iadd.(eq. 2).Iaddend.

Thereafter, the data source 60 changes data signals by first removingthe DAV signal E from line 79 to indicate that data signals on the datalines 78 are no longer valid. The source may then change the datasignals F in accordance with its mode of operation.

At the same time, the data receivers 62, 64, etc. sense the DAV signalon line 79 and reset the DAC signals G, H produced by each of them. Ofcourse, the fastest one of the data receivers to reset its DAC signal Galso removes the DAC signal on line 83 according to the logic equation(2) above, which logic equation is implemented by the gating circuitshown in FIG. 3. Also, the data receivers 62, 64, etc. are then free toreturn to their respective ready-for-data operating conditions which areindicated by the RFD signals K, L produced by the receivers. However, itis only after all data receivers have produced RFD signals K, L that theRFD signal M is produced on line 81 in accordance with the logicequation (1) above, and this indicates the condition of readiness foranother data transfer operating cycle.

Therefore, the apparatus of the present invention permits data to betransferred from one source to a plurality of receivers at a transferrate that is determined only by the response time of the slowestreceivers at each of the transfer operating steps.

I claim:
 1. Data transfer apparatus comprising:source means of datasignals including register means for storing data signals to betransferred .[.;.]. .Iadd., said source means producing a logic signalafter introduction of data signals into the register means and inresponse to an applied control signal, the logic signal beingrepresentative of the validity of data signals to be transferred;.Iaddend. a number of data-receiving means for operating upon applieddata signals from the source means .[.,.]. .Iadd.in response toappearance of said logic signal, .Iaddend.each of said number ofdata-receiving means including means for providing a first outputindication of the operability thereof on applied data signals and meansfor providing a second output indication of the completed acceptance ofapplied data signals .[., independently of the operation thereof on suchapplied data signals.].; means coupling data signals from said sourcemeans to each of said number of data-receiving means; .[. meansresponsive to the appearance of second outputs from all of said numberof data-receiving means for terminating the data signals applied to eachof said number of data-receiving means from said source means; and.].means responsive to the appearance of said first outputs from all ofsaid number of data-receiving means for applying a control signal to.[.a.]. .Iadd.the .Iaddend.source means .[.for introducing new datasignals into said register means for application to all of said numberof data-receiving means..]. .Iadd.; and means responsive to theappearance of second outputs from all of said number of data-receivingmeans for applying a signal to said source means for terminating saidlogic signal and introducing new data signals into said register means..Iaddend. .[.2. Data transfer apparatus as in claim 1 in which saidsource means includes logic means for producing a logic outputrepresentative of the validity of data signals supplied to all of thenumber of data-receiving means from the register means of the sourcemeans, said logic means produces said logic output after new datasignals are introduced into the register means and the first outputsfrom all of the number of data-receiving means ar present; all of saidnumber of data-receiving means accept the data signals from the receivermeans of said source means only in response to the appearance of saidlogic output; and said logic means terminates said logic output inresponse to the appearance of said outputs from all of said number ofdata-receiving means. .].
 3. Data transfer apparatus as in claim 1comprising:a set of data signal lines coupling the register means ofsaid source means to all of said number of data-receiving means andincluding a set of control lines coupled between all of said number ofdata-receiving means and said source means and including a data-valid(DAV) line, a ready-for-data (RFD) line and a data-accepted (DAC) line;first gate means responsive to first outputs from all of said number ofdata-receiving means for applying to the source means a signal on saidRFD line; said source means being responsive to signal on said RFD lineto produce a signal on the DAV line after introduction of data signalsinto the register means for coupling to all of said data-receiving meansover said set of data signal lines; each of said number ofdata-receiving means responds to signal on said DAV line and includesmeans for producing said second outputs after acceptance of such datasignals; and second gate means responsive to the second outputs from allof said data-receiving means for applying to the source means a signalon said DAC line; said source means being responsive to signal on saidDAC line to terminate the signal on said DAV line and to introduce newdata signals into said register means.
 4. Data transfer apparatus as inclaim 3 including detector means responsive to simultaneous presence ofsignals on said RFD and DAC lines for producing an output indication ofthe operating condition of the data transfer apparatus.
 5. Apparatus foroperation in a data transfer system including a number ofdata-responsive units coupled to respond to data and control signals ondata and control channels, the apparatus comprising:source means adaptedto be coupled to data signal channels of a data transfer system fordelivering valid data signals thereto; logic means adapted to receive afirst control signal from a control signal channel of a data transfersystem which is indicative of the condition of readiness of all of thenumber of data-responsive units to receive data signals, said logicmeans being capable of delivering a second control signal to a controlsignal channel following receipt of such first control signal and thesource means having delivered valid data signals, the second controlsignal having one logic state which is indicative of the validity of thedata signals delivered by the source means; and said logic means beingadapted to receive a third control signal from a control signal channelof the data transfer system which is indicative of all of the number ofdata-responsive units having accepted data signals for altering thesecond control signal to a second logic state which indicates that datasignals are not valid and for enabling the source means to deliverupdated data signals to data signal channels.
 6. Apparatus as in claim 5wherein said logic means enables said source means to deliver updateddata signals to data signal channels within the interval from theappearance of a third control signal to the appearance of a secondcontrol signal.
 7. Apparatus as in claim 5 wherein said logic meansenables said source means to deliver updated signals to data signalchannels within the interval from the appearance of the .Iadd.second.Iaddend.control signal in the second logic state which indicates thatdata signals are not valid and the appearance of the second controlsignal in the one logic state which indicates that the delivered datasignals are valid.
 8. Apparatus as in claim 5 comprising error detectingmeans responsive to the appearance simultaneously of the first controlsignal indicative of the condition of readiness and the third controlsignal indicative of all of the number of data-responsive units havingaccepted data signals for producing an output indication of an erroneousoperating condition of the data transfer system.
 9. A data-responsiveunit for operation in a data transfer system including a number of suchdata-responsive units which respond to data signals and control signalson data and control signal channels, the data-responsive unitcomprising:data-receiving means capable of receiving data signals from adata signal channel of a data transfer system and being adapted todeliver to a control signal channel a first control signal having afirst logic state which indicates preparedness to receive data signals;sensing means adapted to be coupled to receive from a control signalchannel of the data transfer system a second control signal having afirst logic state which is indicative of the validity of data signalsfor enabling the data-receiving means to receive the valid data signalsfrom the data signal channel and to change the first control signal to asecond logic state which indicates unpreparedness to receive datasignals; logic means adapted to deliver to a control signal channel athird control signal having a first logic state indicative of havingaccepted the data signals; said sensing means being responsive to saidsecond control signal attaining a second logic state which indicatesthat data signals are not valid for changing the third control signal toa second logic state indicative of completion of a data transfer; andsaid data-receiving means being responsive to the third control signalattaining the second logic state and being prepared to accept new datasignals for changing the first control signal to said first logic state.. A data-responsive unit as in claim 9 wherein said data-receiving meansand said logic means are coupled to inhibit operations thereofsimultaneously in the associated first logic states thereof.
 11. Adata-responsive unit as in claim 9 wherein said data-.[.responsive.]..Iadd.receiving .Iaddend.means includes operative means for manipulatingapplied data signals at a rate substantially independent of the rate atwhich data signals are applied, and including buffer means for retainingapplied data signals for a period required by the operative means tomanipulate data signals, said data-receiving means producing the firstcontrol signal in said first logic state in response to said buffermeans being prepared to accept data, independently of the preparednessof the operative means to manipulate data signals.
 12. A data-responsiveunit as in claim 9 comprising first gating means for cooperating withall similar first gating means associated with all of the remainingnumber of data-responsive units coupled to a common control signalchannel for producing said first control signal on said common controlsignal channel only in response to all of the number of associateddata-receiving means being prepared to accept data signals.
 13. Adata-responsive unit as in claim 9 comprising second gating means forcooperating with all similar second gating means associated with all ofthe remaining number of data-responsive units coupled to a commoncontrol signal channel for producing said third control signal on saidcommon control signal channel only in response to all of the number ofassociated logic means having accepted the data signals.
 14. Datatransfer apparatus as in claim .[.2.]. .Iadd.1 .Iaddend.wherein:saidmeans coupling data signals from said source means applies the datasignals in parallel to each of said plurality of data-receiving means;and a gate circuit is coupled to said source means and to each of saidplurality of data-receiving means fora. terminating the data signalsfrom said source means .[.in response to the appearance in common of allthe second outputs from said plurality of data-receiving means.]., andb. for activating said source means to apply successive data signals inparallel to said plurality of data-receiving means in response to theappearance in common of said .[.first.]. .Iadd.second .Iaddend.outputsfrom said plurality of data-receiving means.
 15. Process fortransferring successive, updated data signals from a source thereof to aplurality of data-signal receivers, each of which indicates itspreparedness to receive data signals and which indicates it completedacceptance of applied data signals, the process comprising the stepsof:applying the data signals in common to all of the plurality ofdata-signal receivers from the source; terminating the application ofthe data signals in common to all of the plurality of data-signalreceivers only in response to all of the plurality of receiversindicating their completed acceptance of the applied data signals; andcontrolling the source to apply successive, updated data signals incommon to all of the plurality of data-signal receivers only in responseto all of the plurality of receivers indicating their preparedness toreceive data signals.
 16. Process according to claim 15 wherein thesource indicates its completion of the updating to successive datasignals, the process comprising the additional steps of:activating allof the plurality of data-signal receivers to receive the updated,successive data signals in common from the source only in response tothe indication therefrom of completion of the updating to the successivedata signals; and terminating the indication by the source of itscompletion of the updating in response to all of the plurality ofdata-signal receivers indicating their acceptance of the applied datasignals.
 17. Process as in claim 16 comprising the additional stepof:producing an error indication in response to the simultaneouspresence of indications that the data-signal receivers are prepared toreceive data signals and have completed acceptance of applied datasignals. .Iadd.
 18. Process for transferring data signals from a sourcethereof to a plurality of data receivers, each of which is enableable toreceive applied data signals in response to a control signal and whichindicates its preparedness to receive data signals and also whichindicates its completed acceptance of applied data signals, the processcomprising the steps of: supplying the data signals in common to all ofthe data-signal receivers from the source; applying a control signal tothe data-signal receivers to enable them to receive the data signalsfrom the source after all of the data-signal receivers indicate theirpreparedness to receive data signals; terminating the control signal todisable the data-signal receivers from receiving the data signals afterall of the data-signal receivers indicate their completed acceptance ofthe data signals; and activating the source to supply successive datasignals in common to all of the data-signal receivers after all of thedata-signal receivers indicate their completed acceptance of the datasignals. .Iaddend..Iadd.
 19. Process as in claim 18 wherein in the stepof applying, the control signal is applied to the data-signal receiversafter all the data-signal receivers indicate their preparedness toreceive the data signals and after a selected delay period following thesupplying of data signals, which delay period is sufficient to allowreflections and transients in the steady-state data signals to decayaway. .Iaddend. .Iadd.
 20. Process for transferring successive, updateddata signals from a source thereof to a plurality of data receivers,each of which is enableable to receive applied data signals in responseto a control signal and which indicates its preparedness to receive datasignals and also which indicates its completed acceptance of applieddata signals, the process comprising the steps of: supplying the datasignals in common to all of the data-signal receivers from the source;applying a control signal to the data-signal receivers to enable them toreceive the data signals from the source after all of the data-signalreceivers indicate their preparedness to receive data signals; restoringall the data-signal receivers to a condition indicative of not beingprepared to receive data signals in response to the application of thecontrol signal thereto; terminating the control signal to disable thedata-signal receivers from receiving the data signals after all of thedata-signal receivers indicate their completed acceptance of the datasignals; restoring all the data-signal receivers to a conditionindicative of not having completed acceptance of applied data signalsafter termination of the control signal; actuating all the data-signalreceivers to a condition indicative of being prepared to receive datasignals after all the data-signal receivers indicate the condition ofnot having completed acceptance of applied data signals; and activatingthe source to supply successive data signals in common to all of thedata-signal receivers after all of the data-signal receivers indicatetheir completed acceptance of the data signals. .Iaddend. .Iadd. 21.Process as in claim 20 wherein in the step of applying, the controlsignal is applied to the data-signal receivers after all the data-signalreceivers indicate their preparedness to receive the data signals andafter a selected delay period following the supplying of data signals,which delay period is sufficient to allow reflections and transients inthe steady-state data signals to decay away. .Iaddend.